CDL Group Seminar

In this seminar, members and guests of our group as well as students preparing a bachelor or master thesis in our group meet weekly to present their work. Furthermore, all participants discuss recent research papers.

Bachelor/Master Seminar
If you want to do a thesis in our group, you will have to attend this seminar. For UdS students: This seminar counts as the Bachelor/Master Seminar.
Reading Group
Other students are cordially invited to discuss recent research papers. These students obtain 3 credit points.

General Information

When: biweekly at Wednesday at 16:00 (sine tempore)
Where: Online, see email

Modus Operandi - Bachelor/Master Seminar

You need to:

The first time you show up at the master seminar, make sure to give us your email address. It will be added to the mailing list and you will receive email notifications before each upcoming session.

After getting the Schein, students need to register their thesis at the Prüfungsamt.

Proposal Regulations

Although the thesis proposal is not part of the master seminar itself, we require a proposal to contain:

A presentation of such a thesis proposal must meet the following requirements:

Research Papers

If we do not have any presentation in the pipeline, we will discuss a recent research paper instead.


Date Speaker Topic Comments
2021-09-08 16:00 Lucas Biehl Characterising Input-Dependent Instruction Timing via Measurements -
2021-09-22 16:00 Alexander Prysinski Detecting Cache Side-Channel Vulnerabilities using Hardware Performance Counters -
2021-09-29 16:00 Anna Welker Determining the Perfect Vectorization Factor -
2021-10-06 16:00 Lukas Gerlach Inferring µop Dependency Graphs from Input-Output Latencies -
2021-11-03 16:00 Tobias Kopp nanoBenchARM: A Performance Analysis Tool for Running Microbenchmarks on ARM Processors -
2021-11-03 16:00 Johannes Kahlen Optimizing cache behavior for fixed memory access programs -
2021-11-10 16:00 Christian Kapp Decoupling Algorithms from Iteration Strategies and Communication for SPMD Constructs in AnyDSL -
2021-12-08 16:00 Till Ganster Visualisierung der Ausführung von Microbenchmarks auf aktuellen Prozessoren Language: German
2022-01-12 16:00 Alexander Prysinski Detecting Cache Side-Channel Vulnerabilities using Hardware Performance Counters -

In cases of questions, do not hesitate to ask Shrey Sharma.