CDL Group Seminar Seminar

In this seminar, members and guests of our group as well as students preparing a bachelor or master thesis in our group meet weekly to present their work. Furthermore, all participants discuss recent research papers.

Bachelor/Master Seminar
If you want to do a thesis in our group, you will have to attend this seminar. For UdS students: This seminar counts as the Bachelor/Master Seminar.
Reading Group
Other students are cordially invited to discuss recent research papers. These students obtain 3 credit points.

General Information

When Thursdays at 14:00 (sine tempore)
Where Room 401, E1 3

The first seminar meeting will be on 18 October 2018.

Modus Operandi - Reading Group


You can find the paper list in our Wiki. In order to access the Wiki you need to register in our GitLab and email Roland Leißa your GitLab username.

Modus Operandi - Bachelor/Master Seminar

You need to:

The first time you show up at the master seminar, make sure to give us your email address. It will be added to the mailing list and you will receive email notifications before each upcoming session.

After getting the Schein, students need to register their thesis at the Pr├╝fungsamt.

Proposal Regulations

Although the thesis proposal is not part of the master seminar itself, we require a proposal to contain:

A presentation of such a thesis proposal must meet the following requirements:


Date Speaker Topic Comments
2018-10-18 14:00 s.t. Kallistos Weis Portable Instruction-Throughput Estimation for Port-Mapping Synthesis Bachelor proposal
2018-11-08 14:00 s.t. - Producing wrong data without doing anything obviously wrong! Paper discussion
2018-11-22 14:00 s.t. Roland Leißa A Compiler-Compiler for DSL Embedding Paper discussion
2018-11-29 14:00 s.t. Wiam Rachid Auto-Vectorizing C++-Code Master talk
2018-12-06 14:00 s.t. Roland Leißa ISA Semantics for ARMv8-A, RISC-V, and CHERI-MIPS Paper discussion
2019-01-10 14:00 s.t. Matthis Kruse An FPGA-Implementation of Sequence Alignment in AnyDSL Bachelor proposal
2019-01-17 14:00 s.t. Fabian Ritter Reverse-Engineering Port-Mappings of Out-of-Order Processors -
2019-01-24 14:00 s.t. Jannic Warken Adaptive Execution of Compiled Queries Paper discussion
2019-01-31 14:00 s.t. Jannis Roth Register Allocation in LLVM Bachelor talk
2019-02-14 14:00 s.t. Dominik Luche Web Browser Based C and MIPS Interpreters for Educational Purposes Bachelor proposal
2019-02-21 14:00 s.t. tba tba -
2019-02-28 14:00 s.t. tba tba -
2019-03-07 14:00 s.t. Matthias Kurtenacker tba Master proposal

In cases of questions, do not hesitate to ask Roland Leißa.