Contact

Tel	_	+49 681 302-57522
Mail	_
Address	_	Saarland Informatics Campus Building E1 3 66123 Saarbrücken Germany
Room	_	403
ORCID	_	0000-0003-2656-9863
	_

Joachim Meyer

Curriculum Vitae

Research Interests

High performance computing
Heterogeneous compute
Parallel programming
Compilation techniques to improve all of the above

Projects

AdaptiveCpp: An implementation of the SYCL standard, providing high-performance access to GPUs and CPUs from all major vendors.
AnyDSL: A framework to develop heterogeneous, high-performance domain-specific languages with an emphasis on extensiblity.
HPC@UdS: Advancing HPC at Saarland University and providing services as part of NHR SW.

Teaching

Lecturer's Assistant

Compiler Construction (WS2024/25)
Compiler Construction (WS2025/26)

NHR Workshops

Community Involvement

IWOCL'24: Program Commitee
IWOCL'25: Program Commitee
IWOCL'26: Program Commitee

Publications

Journal Papers

MimIR: An Extensible and Type-Safe Intermediate Representation for the DSL Age
Leißa, R., Ullrich, M., Meyer, J. and Hack, S.
Proc. ACM Program. Lang., 9 (POPL), 2025. [doi] [url] [bib]

@article{Mimir:10.1145/3704840,
   author = {Lei\ss{}a, Roland and Ullrich, Marcel and Meyer, Joachim and Hack, Sebastian},
   title = {MimIR: An Extensible and Type-Safe Intermediate Representation for the DSL Age},
   year = {2025},
   issue_date = {January 2025},
   publisher = {Association for Computing Machinery},
   address = {New York, NY, USA},
   volume = {9},
   number = {POPL},
   url = {https://doi.org/10.1145/3704840},
   doi = {10.1145/3704840},
   abstract = {Traditional compilers, designed for optimizing low-level code, fall short when dealing with modern, computation-heavy applications like image processing, machine learning, or numerical simulations. We show that in all three studies, MimIR produces code that has state-of-the-art performance.},
   journal = {Proc. ACM Program. Lang.},
   month = jan,
   articleno = {4},
   numpages = {31},
   keywords = {compiler intermediate representations, dependent types, lambda-calculus}
 }

Workshop Papers

Implementation Techniques for SPMD Kernels on CPUs
Meyer, J., Alpay, A., Hack, S., Fröning, H. and Heuveline, V.
Proceedings of the 2023 International Workshop on OpenCL, Association for Computing Machinery, 2023. [doi] [url] [pdf] [bib]

@inproceedings{Meyer:IWOCL23:10.1145/3585341.3585342,
   author = {Meyer, Joachim and Alpay, Aksel and Hack, Sebastian and Fr\"oning, Holger and Heuveline, Vincent},
   title = {Implementation Techniques for SPMD Kernels on CPUs},
   year = {2023},
   isbn = {9798400707452},
   publisher = {Association for Computing Machinery},
   address = {New York, NY, USA},
   url = {https://doi.org/10.1145/3585341.3585342},
   webpdf = {https://dl.acm.org/doi/pdf/10.1145/3585341.3585342},
   doi = {10.1145/3585341.3585342},
   abstract = {More and more frameworks and simulations are developed using heterogeneous programming models such as OpenCL, SYCL, CUDA, or HIP. A significant hurdle to mapping these models to CPUs in a performance-portable manner is that implementing work-group barriers for such kernels requires providing forward-progress guarantees so that all work-items can reach the barrier. This work provides guidance for implementations of single-program multiple-data (SPMD) programming models, such as OpenCL, SYCL, CUDA, or HIP, on non-SPMD devices, such as CPUs. We discuss the trade-offs of multiple approaches to handling work-group-level barriers. We present our experience with the integration of two known compiler-based approaches for low-overhead work-group synchronization on CPUs. Thereby we discuss a general design flaw in deep loop fission approaches, as used in the popular Portable Computing Language (PoCL) project, that makes them miscompile certain kernels. For our evaluation, we integrate PoCL’s “loopvec” kernel compiler into hipSYCL and implement continuation-based synchronization (CBS) in the same. We compare both against hipSYCL’s library-only fiber implementation using diverse hardware: we use recent AMD Rome and Intel Icelake server CPUs but also two Arm server CPUs, namely Fujitsu’s A64FX and Marvell’s ThunderX2. We show that compiler-based approaches outperform library-only implementations by up to multiple orders of magnitude. Further, we adapt our CBS implementation into PoCL and compare it against its loopvec approach in both, PoCL and hipSYCL. We find that our implementation of CBS, while being more general than PoCL’s approach, gives comparable performance in PoCL and even surpasses it in hipSYCL. Therefore we recommend its use in general.},
   booktitle = {Proceedings of the 2023 International Workshop on OpenCL},
   articleno = {1},
   numpages = {12},
   keywords = {CPU, performance portability, barriers, OpenCL, compilation, synchronization, heterogeneous computing, SYCL},
   location = {Cambridge, United Kingdom},
   series = {IWOCL '23}
 }

Evaluation of Modern GPGPU Technologies for Image Processing
Meyer, J.
Proceedings of the International Workshop on OpenCL, Association for Computing Machinery, 2020. [doi] [url] [bib]

@inproceedings{Meyer:IWOCL20:10.1145/3388333.3388645,
 author = {Meyer, Joachim},
 title = {Evaluation of Modern GPGPU Technologies for Image Processing},
 year = {2020},
 isbn = {9781450375313},
 publisher = {Association for Computing Machinery},
 address = {New York, NY, USA},
 url = {https://doi.org/10.1145/3388333.3388645},
 doi = {10.1145/3388333.3388645},
 booktitle = {Proceedings of the International Workshop on OpenCL},
 articleno = {2},
 numpages = {2},
 keywords = {CUDA, Vulkan, SYCL, OpenCL, Image Processing, GPGPU, Evaluation},
 location = {Munich, Germany},
 series = {IWOCL '20}
 }

MSc Thesis

Compiler-assisted optimizations for data-parallel paradigms in hipSYCL
Meyer, J.
M.Sc. Thesis, Heidelberg University, 2021. [pdf] [bib]

@MASTERSTHESIS{Meyer:2021:MSc,
     author  = {Joachim Meyer},
     title   = {{Compiler-assisted optimizations for data-parallel paradigms in hipSYCL}},
     school  = {Heidelberg University},
     year    = {2021},
     month   = {November},
     webpdf  = {http://www.cdl.uni-saarland.de/publications/theses/meyer_msc.pdf}
 }

Other

Compiler-Aided Nd-Range Parallel-for Implementations on CPU in HipSYCL
Meyer, J., Alpay, A., Fröning, H. and Heuveline, V.
[doi] [url] [bib]

@OTHER{Meyer:IWOCL22:10.1145/3529538.3530216,
   author = {Meyer, Joachim and Alpay, Aksel and Fr\"oning, Holger and Heuveline, Vincent},
   title = {Compiler-Aided Nd-Range Parallel-for Implementations on CPU in HipSYCL},
   year = {2022},
   isbn = {9781450396585},
   publisher = {Association for Computing Machinery},
   address = {New York, NY, USA},
   url = {https://doi.org/10.1145/3529538.3530216},
   doi = {10.1145/3529538.3530216},
   abstract = {With heterogeneous programming continuously on the rise, performance portability is still to be improved. SYCL provides the nd-range parallel-for paradigm for writing data-parallel kernels. This model allows barriers for group-local synchronization, similar to CUDA and OpenCL kernels. GPUs provide efficient means to model this, but on CPUs the necessary forward-progress guarantees require the use of many (lightweight) threads in library-only SYCL implementations, rendering the nd-range parallel-for unacceptably inefficient. By adopting two compiler-based approaches solving this, the present work improves the performance of the nd-range parallel-for in hipSYCL for CPUs by up to multiple orders of magnitude on various CPU architectures. The two alternatives are compared with regard to their functional correctness and performance. By upstreaming one of the variants, hipSYCL is the first SYCL implementation to provide a well performing nd-range parallel-for on CPU, without requiring an available OpenCL runtime.},
   booktitle = {International Workshop on OpenCL},
   articleno = {28},
   numpages = {3},
   keywords = {performance portability, SYCL, OpenCL, heterogeneous, nd-range, CPU, LLVM, compilation},
   location = {Bristol, United Kingdom, United Kingdom},
   series = {IWOCL'22}
 }